insn does not satisfy its constraints

[Omar Torres]

Hi All,
  I am getting the error message bellow while hacking my gcc backend.
Any suggestions on how to fix this?

error: insn does not satisfy its constraints:
(insn 25 50 26 2 (set (reg:HI 1 %r0 [33])
         (plus:HI (mem/s/j:HI (plus:HI (reg:HI 3 %r2)
                     (reg/v/f:HI 11 %i2h [orig:28 cell ] [28])) [0
<variable>.dod S2 A8])
             (reg:HI 1 %r0 [43]))) 8 {*addhi3} (insn_list:REG_DEP_TRUE 3
(insn_list:REG_DEP_TRUE 24 (nil)))
     (nil))


The md description for this instruction is:

;; addhi3
(define_expand "addhi3"
   [(set (match_operand:HI 0 "register_operand"             "")
        (plus:HI (match_operand:HI 1 "cool_addhi_operand"  "")
                 (match_operand:HI 2 "cool_addhi_operand"  "")))]
   ""
   "")

(define_insn "*addhi3"
   [(set (match_operand:HI 0 "register_operand"            "=r ,r  ,r")
        (plus:HI (match_operand:HI 1 "cool_addhi_operand" "%0 ,rim,r")
                 (match_operand:HI 2 "cool_addhi_operand" "rim,0  ,r")))]
   ""
  {
    operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, 1);
    operands[4] = simplify_gen_subreg (QImode, operands[0], HImode, 0);

    operands[5] = simplify_gen_subreg (QImode, operands[1], HImode, 1);
    operands[6] = simplify_gen_subreg (QImode, operands[1], HImode, 0);

    operands[7] = simplify_gen_subreg (QImode, operands[2], HImode, 1);
    operands[8] = simplify_gen_subreg (QImode, operands[2], HImode, 0);

    if (!which_alternative)
        return "ADD\t%3,%7\n\tADDC\t%4,%8";
    else if (1 == which_alternative)
        return "ADD\t%3,%5\n\tADDC\t%4,%6";
    else
        return "ADD\t%3,%5,%8\n\tADDC\t%4,%5,%8";
   })

Regards,
  -Omar

[shafi]

>Hi All,
>  I am getting the error message bellow while hacking my gcc backend.
>Any suggestions on how to fix this?
>
>error: insn does not satisfy its constraints:
>(insn 25 50 26 2 (set (reg:HI 1 %r0 [33])
>         (plus:HI (mem/s/j:HI (plus:HI (reg:HI 3 %r2)
>                     (reg/v/f:HI 11 %i2h [orig:28 cell ] [28])) [0
><variable>.dod S2 A8])
>             (reg:HI 1 %r0 [43]))) 8 {*addhi3} (insn_list:REG_DEP_TRUE 3
>(insn_list:REG_DEP_TRUE 24 (nil)))
>     (nil))
>

   Operand 0 is a register
   Operand 1 is a memory
   Operand 2 is a register

>
>The md description for this instruction is:
>
>;; addhi3
>(define_expand "addhi3"
>   [(set (match_operand:HI 0 "register_operand"             "")
> (plus:HI (match_operand:HI 1 "cool_addhi_operand"  "")
> (match_operand:HI 2 "cool_addhi_operand"  "")))]
>   ""
>   "")
>
>(define_insn "*addhi3"
>   [(set (match_operand:HI 0 "register_operand"            "=r ,r  ,r")
> (plus:HI (match_operand:HI 1 "cool_addhi_operand" "%0 ,rim,r")
> (match_operand:HI 2 "cool_addhi_operand" "rim,0  ,r")))]
>   ""
 
   Do you have an option where operand 0 is reg and operand 1 is mem and operand 2 is reg?
   I am not sure what rim is for?

 Shafi

[Omar Torres]

shafi wrote:

>    Operand 0 is a register
>    Operand 1 is a memory
>    Operand 2 is a register
>
>
>> The md description for this instruction is:
>>
>> ;; addhi3
>> (define_expand "addhi3"
>>   [(set (match_operand:HI 0 "register_operand"             "")
>> (plus:HI (match_operand:HI 1 "cool_addhi_operand"  "")
>> (match_operand:HI 2 "cool_addhi_operand"  "")))]
>>   ""
>>   "")
>>
>> (define_insn "*addhi3"
>>   [(set (match_operand:HI 0 "register_operand"            "=r ,r  ,r")
>> (plus:HI (match_operand:HI 1 "cool_addhi_operand" "%0 ,rim,r")
>> (match_operand:HI 2 "cool_addhi_operand" "rim,0  ,r")))]
>>   ""
>>
>
>    Do you have an option where operand 0 is reg and operand 1 is mem and
> operand 2 is reg?
>

My purpose is to describe the three possible scenarios:
1)  Operand 0 is a register
     Operand 1 is the same register as operand 0
     Operand 2 is a register, immediate or memory

2)  Operand 0 is a register
     Operand 1 is a register, immediate or memory
      Operand 2 is the same register as operand 0

3)  Operand 0 is a register
     Operand 2 is a register
     Operand 3 is also a register


>    I am not sure what rim is for?
>
rim = is a short cut for r, m, i. I think is is allow to mix several
constrains like this, right?


Thanks,
-Omar

[shafi]

----- Original Message ----

> From: Omar Torres <gcc.omar@...>
> To: shafitvm@...
> Cc: gcc@...
> Sent: Saturday, August 30, 2008 12:11:36 AM
> Subject: Re: insn does not satisfy its constraints
>
> shafi wrote:
> >    Operand 0 is a register
> >    Operand 1 is a memory
> >    Operand 2 is a register
> >
> >
> >> The md description for this instruction is:
> >>
> >> ;; addhi3
> >> (define_expand "addhi3"
> >>   [(set (match_operand:HI 0 "register_operand"             "")
> >>     (plus:HI (match_operand:HI 1 "cool_addhi_operand"  "")
> >>          (match_operand:HI 2 "cool_addhi_operand"  "")))]
> >>   ""
> >>   "")
> >>
> >> (define_insn "*addhi3"
> >>   [(set (match_operand:HI 0 "register_operand"            "=r ,r  ,r")
> >>     (plus:HI (match_operand:HI 1 "cool_addhi_operand" "%0 ,rim,r")
> >>          (match_operand:HI 2 "cool_addhi_operand" "rim,0  ,r")))]
> >>   ""
> >>
> >
> >    Do you have an option where operand 0 is reg and operand 1 is mem and
> > operand 2 is reg?
> >
> My purpose is to describe the three possible scenarios:
> 1)  Operand 0 is a register
>      Operand 1 is the same register as operand 0
>      Operand 2 is a register, immediate or memory
>
> 2)  Operand 0 is a register
>      Operand 1 is a register, immediate or memory
>       Operand 2 is the same register as operand 0
>
> 3)  Operand 0 is a register
>      Operand 2 is a register
>      Operand 3 is also a register
>
>
> >    I am not sure what rim is for?
> >
> rim = is a short cut for r, m, i. I think is is allow to mix several
> constrains like this, right?
>

   So rim is a user define constraint. Then i think you may want to look properly into EXTRA_CONSTRAINT_STR. Probably this is where you might be going wrong.

HTH
Shafi