make verilate error (EAN6/ESP5 ORPSoC with Verilator)

[swaka]

Hi,

I try to run EAN6 (ORPSoc with Verilator) according to ESP5 document.
"make simulate ..." works fine.
But "make verilate ..." does not work.


I modified some codes according to ESP5 document.

% make verilate COMMAND_FILE=cf-baseline.scr VFLAGS="-Wno-lint
-Wno-COMBDLY -Wno-UNOPTFLAT -language 1364-2001"

cd sim/src && ln -s ../../local/sw/dhry/dhry-icdc-O2.hex flash.in
cd verilator-model && time -p make
make[1]: Entering directory
`/home/usr/swaka/work/sc/or1k/embecosm-esp5-or1k-verilator-1.0/verilator-model'
Makefile:121: OrpsocAccess.d: No such file or directory
Makefile:121: TraceSC.d: No such file or directory
Makefile:122: Vorpsoc_fpga_top__ALLcls.d: No such file or directory
Makefile:122: Vorpsoc_fpga_top__ALLsup.d: No such file or directory
Makefile:122: Vorpsoc_fpga_top__ver.d: No such file or directory
verilator -Wno-lint -Wno-COMBDLY -Wno-UNOPTFLAT -language 1364-2001
-Mdir . -sc -f v-processed.scr
Can't exec "/home/eda/jeda/verilator/verilator_bin": No such file or
directory at /home/eda/jeda/verilator/3701/bin/verilator line 116.
%Error: verilator: Misinstalled, or VERILATOR_ROOT might need to be in
environment
%Error: Command Failed /home/eda/jeda/verilator/verilator_bin
-Wno-lint -Wno-COMBDLY -Wno-UNOPTFLAT -language 1364-2001 -Mdir . -sc
-f v-processed.scr
make[1]: *** [Vorpsoc_fpga_top.mk] Error 2
make[1]: Leaving directory
`/home/usr/swaka/work/sc/or1k/embecosm-esp5-or1k-verilator-1.0/verilator-model'



After I manually created *.d, a following error still occurs.

make[2]: Entering directory
`/home/usr/swaka/work/sc/or1k/embecosm-esp5-or1k-verilator-1.0/verilator-model'
g++  -I. -MMD -I/home/eda/jeda/verilator/verilator-3.701/include
-DVL_PRINTF=printf -DVM_TRACE=0 -DVM_COVERAGE=0      
-I/home/eda/jeda/SC/RHE4/32/systemc-2.2.0/include -c -o OrpsocAccess.o
OrpsocAccess.cpp
OrpsocAccess.cpp:32:41: Vorpsoc_fpga_top_or1200_cpu.h: No such file or
directory
OrpsocAccess.cpp:33:42: Vorpsoc_fpga_top_or1200_ctrl.h: No such file
or directory
OrpsocAccess.cpp:34:40: Vorpsoc_fpga_top_or1200_rf.h: No such file or
directory
OrpsocAccess.cpp:35:51: Vorpsoc_fpga_top_or1200_rfram_generic.h: No
such file or directory
OrpsocAccess.cpp:36:41: Vorpsoc_fpga_top_or1200_top.h: No such file or
directory
OrpsocAccess.cpp:37:46: Vorpsoc_fpga_top_orpsoc_fpga_top.h: No such
file or directory

There were no code such as "Vorpsoc_fpga_top_or1200_cpu.h".

Could you give me some comments?

My environment :
RHEL4 32bit
Verilator :  3.701
IVerilog : 0.8.7

Regards,
swaka
_______________________________________________
http://www.opencores.org/mailman/listinfo/openrisc

[Jeremy Bennett-4]

On Wed, 2009-03-04 at 07:27 +0100, swaka@... wrote:
> Hi,
>
> I try to run EAN6 (ORPSoc with Verilator) according to ESP5 document.
> "make simulate ..." works fine.

Hi Swaka,

That bit's good news...

> But "make verilate ..." does not work.

... not such good news. Suggestions below.

>
> I modified some codes according to ESP5 document.
>
> % make verilate COMMAND_FILE=cf-baseline.scr VFLAGS="-Wno-lint
> -Wno-COMBDLY -Wno-UNOPTFLAT -language 1364-2001"
>
> cd sim/src && ln -s ../../local/sw/dhry/dhry-icdc-O2.hex flash.in
> cd verilator-model && time -p make
> make[1]: Entering directory
> `/home/usr/swaka/work/sc/or1k/embecosm-esp5-or1k-verilator-1.0/verilator-model'
> Makefile:121: OrpsocAccess.d: No such file or directory
> Makefile:121: TraceSC.d: No such file or directory
> Makefile:122: Vorpsoc_fpga_top__ALLcls.d: No such file or directory
> Makefile:122: Vorpsoc_fpga_top__ALLsup.d: No such file or directory
> Makefile:122: Vorpsoc_fpga_top__ver.d: No such file or directory

These are just warnings from make that it cannot find the dependency
files. It then carries on and creates them. So the warnings can be
ignored. I should add a note about this warning to the application note.

I'm not a great expert on make. I'd welcome suggestions for a way to
turn off these warnings or a better way of using dependency files. My
code is taken straight from the make manual.

> verilator -Wno-lint -Wno-COMBDLY -Wno-UNOPTFLAT -language 1364-2001
> -Mdir . -sc -f v-processed.scr
> Can't exec "/home/eda/jeda/verilator/verilator_bin": No such file or
> directory at /home/eda/jeda/verilator/3701/bin/verilator line 116.
> %Error: verilator: Misinstalled, or VERILATOR_ROOT might need to be in
> environment
> %Error: Command Failed /home/eda/jeda/verilator/verilator_bin
> -Wno-lint -Wno-COMBDLY -Wno-UNOPTFLAT -language 1364-2001 -Mdir . -sc
> -f v-processed.scr

This seems to be the problem. Looks like Verilator hasn't installed
properly. Since we are generating SystemC you need to ensure that you
have installed Verilator AND SystemPerl and VerilogPerl. You also need
to make sure the VERILATOR_ROOT environment variable is pointing to the
root of the *source* directory where you unpacked Verilator.

As an initial test check that 'verilator --version' works OK from the
command line.

> make[1]: *** [Vorpsoc_fpga_top.mk] Error 2
> make[1]: Leaving directory
> `/home/usr/swaka/work/sc/or1k/embecosm-esp5-or1k-verilator-1.0/verilator-model'
>
>
>
> After I manually created *.d, a following error still occurs.
>
> make[2]: Entering directory
> `/home/usr/swaka/work/sc/or1k/embecosm-esp5-or1k-verilator-1.0/verilator-model'
> g++  -I. -MMD -I/home/eda/jeda/verilator/verilator-3.701/include
> -DVL_PRINTF=printf -DVM_TRACE=0 -DVM_COVERAGE=0      
> -I/home/eda/jeda/SC/RHE4/32/systemc-2.2.0/include -c -o OrpsocAccess.o
> OrpsocAccess.cpp
> OrpsocAccess.cpp:32:41: Vorpsoc_fpga_top_or1200_cpu.h: No such file or
> directory
> OrpsocAccess.cpp:33:42: Vorpsoc_fpga_top_or1200_ctrl.h: No such file
> or directory
> OrpsocAccess.cpp:34:40: Vorpsoc_fpga_top_or1200_rf.h: No such file or
> directory
> OrpsocAccess.cpp:35:51: Vorpsoc_fpga_top_or1200_rfram_generic.h: No
> such file or directory
> OrpsocAccess.cpp:36:41: Vorpsoc_fpga_top_or1200_top.h: No such file or
> directory
> OrpsocAccess.cpp:37:46: Vorpsoc_fpga_top_orpsoc_fpga_top.h: No such
> file or directory
>
> There were no code such as "Vorpsoc_fpga_top_or1200_cpu.h".

These are all files created by Verilator, so it looks like Verilator has
yet to be executed. I think manual creation of the dependency files may
have confused make.

Try starting again ('make clean' should work). I think the key problem
is your environment is not correctly picking up the Verilator tool as
noted above.

HTH,


Jeremy

>
> Could you give me some comments?
>
> My environment :
> RHEL4 32bit
> Verilator :  3.701
> IVerilog : 0.8.7
>
> Regards,
> swaka
> _______________________________________________
> http://www.opencores.org/mailman/listinfo/openrisc

--
Tel:      [phone]
Cell:     [phone]
SkypeID: jeremybennett
Email:   jeremy.bennett@...
Web:     www.embecosm.com


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[swaka]

Hi,

Thank you for your quick support.

After some modifications, I could run "make verilater ...".
Let me clarify my modifications.


1. make software
1.1
added "#define OR1K 1" for support.c/int.c/dhry.c
1.2
modified local/sw/dhry/Makefile
common = ../support/libsupport.a <path to
cross_compiler>/or32-uclinux/lib/gcc/or32-uclinux/4.2.2/libgcc.a


2. make verilator
2.1 compile error after verilator
verilated.cpp
OrpsocAccess.cpp
TraceSC.cpp

g++  -I. -MMD -I/home/eda/jeda/verilator/verilator-3.700/include
-DVL_PRINTF=printf -DVM_TRACE=0 -DVM_COVERAGE=0
-I/home/eda/jeda/SC/RHE4/32/systemc-2.2.0/include linux -c -o TraceSC.o
TraceSC.cpp
g++: linux: No such file or directory
make[2]: *** [TraceSC.o] Error 1

But compile again, then pass. I do not know the reason.


Regards,
swaka

-------- Original Message --------
Subject: Re: [openrisc] make verilate error (EAN6/ESP5 ORPSoC with
Verilator)
From: Jeremy Bennett <jeremy.bennett@...>
To: List about OpenRISC project <openrisc@...>
Date: 2009/03/04 19:07

> On Wed, 2009-03-04 at 07:27 +0100, swaka@... wrote:
>> Hi,
>>
>> I try to run EAN6 (ORPSoc with Verilator) according to ESP5 document.
>> "make simulate ..." works fine.
>
> Hi Swaka,
>
> That bit's good news...
>
>> But "make verilate ..." does not work.
>
> ... not such good news. Suggestions below.
>> I modified some codes according to ESP5 document.
>>
>> % make verilate COMMAND_FILE=cf-baseline.scr VFLAGS="-Wno-lint
>> -Wno-COMBDLY -Wno-UNOPTFLAT -language 1364-2001"
>>
>> cd sim/src && ln -s ../../local/sw/dhry/dhry-icdc-O2.hex flash.in
>> cd verilator-model && time -p make
>> make[1]: Entering directory
>> `/home/usr/swaka/work/sc/or1k/embecosm-esp5-or1k-verilator-1.0/verilator-model'
>> Makefile:121: OrpsocAccess.d: No such file or directory
>> Makefile:121: TraceSC.d: No such file or directory
>> Makefile:122: Vorpsoc_fpga_top__ALLcls.d: No such file or directory
>> Makefile:122: Vorpsoc_fpga_top__ALLsup.d: No such file or directory
>> Makefile:122: Vorpsoc_fpga_top__ver.d: No such file or directory
>
> These are just warnings from make that it cannot find the dependency
> files. It then carries on and creates them. So the warnings can be
> ignored. I should add a note about this warning to the application note.
>
> I'm not a great expert on make. I'd welcome suggestions for a way to
> turn off these warnings or a better way of using dependency files. My
> code is taken straight from the make manual.
>
>> verilator -Wno-lint -Wno-COMBDLY -Wno-UNOPTFLAT -language 1364-2001
>> -Mdir . -sc -f v-processed.scr
>> Can't exec "/home/eda/jeda/verilator/verilator_bin": No such file or
>> directory at /home/eda/jeda/verilator/3701/bin/verilator line 116.
>> %Error: verilator: Misinstalled, or VERILATOR_ROOT might need to be in
>> environment
>> %Error: Command Failed /home/eda/jeda/verilator/verilator_bin
>> -Wno-lint -Wno-COMBDLY -Wno-UNOPTFLAT -language 1364-2001 -Mdir . -sc
>> -f v-processed.scr
>
> This seems to be the problem. Looks like Verilator hasn't installed
> properly. Since we are generating SystemC you need to ensure that you
> have installed Verilator AND SystemPerl and VerilogPerl. You also need
> to make sure the VERILATOR_ROOT environment variable is pointing to the
> root of the *source* directory where you unpacked Verilator.
>
> As an initial test check that 'verilator --version' works OK from the
> command line.
>
>> make[1]: *** [Vorpsoc_fpga_top.mk] Error 2
>> make[1]: Leaving directory
>> `/home/usr/swaka/work/sc/or1k/embecosm-esp5-or1k-verilator-1.0/verilator-model'
>>
>>
>>
>> After I manually created *.d, a following error still occurs.
>>
>> make[2]: Entering directory
>> `/home/usr/swaka/work/sc/or1k/embecosm-esp5-or1k-verilator-1.0/verilator-model'
>> g++  -I. -MMD -I/home/eda/jeda/verilator/verilator-3.701/include
>> -DVL_PRINTF=printf -DVM_TRACE=0 -DVM_COVERAGE=0      
>> -I/home/eda/jeda/SC/RHE4/32/systemc-2.2.0/include -c -o OrpsocAccess.o
>> OrpsocAccess.cpp
>> OrpsocAccess.cpp:32:41: Vorpsoc_fpga_top_or1200_cpu.h: No such file or
>> directory
>> OrpsocAccess.cpp:33:42: Vorpsoc_fpga_top_or1200_ctrl.h: No such file
>> or directory
>> OrpsocAccess.cpp:34:40: Vorpsoc_fpga_top_or1200_rf.h: No such file or
>> directory
>> OrpsocAccess.cpp:35:51: Vorpsoc_fpga_top_or1200_rfram_generic.h: No
>> such file or directory
>> OrpsocAccess.cpp:36:41: Vorpsoc_fpga_top_or1200_top.h: No such file or
>> directory
>> OrpsocAccess.cpp:37:46: Vorpsoc_fpga_top_orpsoc_fpga_top.h: No such
>> file or directory
>>
>> There were no code such as "Vorpsoc_fpga_top_or1200_cpu.h".
>
> These are all files created by Verilator, so it looks like Verilator has
> yet to be executed. I think manual creation of the dependency files may
> have confused make.
>
> Try starting again ('make clean' should work). I think the key problem
> is your environment is not correctly picking up the Verilator tool as
> noted above.
>
> HTH,
>
>
> Jeremy
>
>> Could you give me some comments?
>>
>> My environment :
>> RHEL4 32bit
>> Verilator :  3.701
>> IVerilog : 0.8.7
>>
>> Regards,
>> swaka
>> _______________________________________________
>> http://www.opencores.org/mailman/listinfo/openrisc

_______________________________________________
http://www.opencores.org/mailman/listinfo/openrisc

[Jeremy Bennett-4]

On Thu, 2009-03-05 at 00:12 +0900, Shinji Wakatsuki wrote:

> Hi,
>
> Thank you for your quick support.
>
> After some modifications, I could run "make verilater ...".
> Let me clarify my modifications.
>
>
> 1. make software
> 1.1
> added "#define OR1K 1" for support.c/int.c/dhry.c
> 1.2
> modified local/sw/dhry/Makefile
> common = ../support/libsupport.a <path to
> cross_compiler>/or32-uclinux/lib/gcc/or32-uclinux/4.2.2/libgcc.a

Hi Swaka,

The library in sw/support has a small boot loader which does some
initialization of caches etc. It is also designed to be loaded as a
flash image at 0x40000000 and then copy down to RAM at 0x00000000.

I'm not sure what initialization is in libgcc.a. It may all work just
fine.

>
> 2. make verilator
> 2.1 compile error after verilator
> verilated.cpp
> OrpsocAccess.cpp
> TraceSC.cpp
>
> g++  -I. -MMD -I/home/eda/jeda/verilator/verilator-3.700/include
> -DVL_PRINTF=printf -DVM_TRACE=0 -DVM_COVERAGE=0
> -I/home/eda/jeda/SC/RHE4/32/systemc-2.2.0/include linux -c -o TraceSC.o
> TraceSC.cpp
> g++: linux: No such file or directory
> make[2]: *** [TraceSC.o] Error 1
>
> But compile again, then pass. I do not know the reason.
>

I ran into something similar in the past. Do you have TARGET_ARCH
defined to 'linux' for SystemC? That seems to conflict with Verilator.
You may find the problem goes away if you undefine TARGET_ARCH.

HTH,


Jeremy

--
Tel:      [phone]
Cell:     [phone]
SkypeID: jeremybennett
Email:   jeremy.bennett@...
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[vinut]

Hi,

I am also facing the same problem with make verilate..
I am getting an error like this..Not exactly what swaka had..
Pleae reply..
cd sim/src && ln -s ../../local/sw/dhry/dhry-icdc-O2.hex flash.in
cd verilator-model && time -p make
make[1]: Entering directory `/home/vinitha/simulations/Or1200_1/orpsoc-models-1.0/verilator-model'
Makefile:121: OrpsocAccess.d: No such file or directory
Makefile:121: TraceSC.d: No such file or directory
Makefile:122: Vorpsoc_fpga_top__ALLcls.d: No such file or directory
Makefile:122: Vorpsoc_fpga_top__ALLsup.d: No such file or directory
Makefile:122: Vorpsoc_fpga_top__ver.d: No such file or directory
/bin/sh: cf-base-line.scr: No such file or directory
make[1]: *** [Vorpsoc_fpga_top.mk] Error 1
make[1]: Leaving directory `/home/vinitha/simulations/Or1200_1/orpsoc-models-1.0/verilator-model'
real 0.00
user 0.00
sys 0.00
make: *** [model] Error 2


Regards
Vinitha