On Thu, 2009-02-26 at 05:46 +0100,
swaka@... wrote:
> Hi,
>
> To support model endianness != host endianness,
> A following modification is necessary.
>
> void
> Or1ksimSC::doTrans( tlm::tlm_generic_payload &trans )
> {
> if( m_endianness != tlm::get_host_endianness() ){
> tlm::tlm_to_hostendian_word<uint8_t>(&trans,4);
> }
>
> wait( sc_core::sc_time( or1ksim_get_time_period(), sc_core::SC_SEC ));
> or1ksim_set_time_point();
> sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
> dataBus->b_transport( trans, delay );
> wait( delay );
>
> if( m_endianness != tlm::get_host_endianness() ){
> tlm::tlm_from_hostendian_word<uint8_t>(&trans,4);
> }
> } // doTrans()
>
Hi Swaka,
I spent some time looking at the SystemC TLM 2.0 endianness support
routines in the standard. They are not easy to understand.
I don't believe this is necessary in this case. My understanding of the
tlm_to_hostendian function is that it adapts for different width TLM
ports, taking into account host endianness.
Both the model of the UART and the transaction payload are host-endian.
The port width to the UART (32 bits) is also the same as the port width
from Or1ksim, even though the UART only uses 1 byte at a time.
Under these circumstances tlm_to_hostendian_word is not needed. Your
example would be appropriate if the UART had only an 8-bit bus.
This is a highly confusing part of the TLM 2.0 standard, but I believe I
have the correct interpretation.
ATB,
Jeremy
--
Tel: +44 (1202) 416955
Cell: +44 (7970) 676050
SkypeID: jeremybennett
Email:
jeremy.bennett@...
Web: www.embecosm.com
_______________________________________________
http://www.opencores.org/mailman/listinfo/openrisc
