Nabble - port-arc

5.0 mipsel 2009Q1 packages binary

2009-09-08T08:31:03Z

I wrote:

> My RaQ2 has been working on 2009Q1 pkgsrc binary build since
> 5.0 release date and it's still in progress at ~82% (6548/7962),
> but I've uploaded binaries built till last week:
>
> ftp://ftp.NetBSD.org/pub/pkgsrc/packages/NetBSD/mipsel/5.0_2009Q1/

Now bulkbuild on RaQ2 is complete and I've put binaries again:
ftp://ftp.NetBSD.org/pub/pkgsrc/packages/NetBSD/mipsel/5.0_2009Q1/

Note editors/emacs (emacs-22.3nb1) in pkgsrc-2009Q1 is broken on mips,
so I've also built patched packages separately for popular demand:
ftp://ftp.NetBSD.org/pub/NetBSD/misc/tsutsui/mipsel/emacs-22.3nb1.tgz
ftp://ftp.NetBSD.org/pub/NetBSD/misc/tsutsui/mipsel/emacs-nox11-22.3nb1.tgz

> To use binaries, set or enable PKG_PATH environment,
> which is commented out in /root/.cshrc
>
> #setenv PKG_PATH "ftp://ftp.netbsd.org/pub/pkgsrc/packages/NetBSD/`uname -m`/5.0/All"
>
> or /root/.profile
>
> #export PKG_PATH="ftp://ftp.netbsd.org/pub/pkgsrc/packages/NetBSD/$(uname -m)/5.0/All"
>
> (note there are appropriate symlinks for version and port strings)
> and just type
> # pkg_add tcsh
> # pkg_add perl
> etc.
>
> Note 5.0 binaries should work fine on 5.0.1.
> pkg_add(1) command might warn about version mismatch,
> but generally it's harmless if running system is newer
> than package's version.
>
> See the pkgsrc guide for more details:
> http://www.NetBSD.org/docs/pkgsrc/using.html#using-pkg
> (sorry no openoffice2 binary for mips)

---
Izumi Tsutsui

Morre o assassino da garota Eloá.

2009-01-19T06:52:11Z

Morre o assassino da garota Eloá.

O jovem que chamou a atenção da mídia por vários dias,
foi encontrado morto em sua cela.

Lindemberg Alves manteve por mais de cem horas como refém
em um apartamento, sua ex namorada Eloá Cristina e sua amiga
Nayara, o sequestro teve inicio dia 13 de outubro 2008 e
acabou na morte da garota Eloá dias depois.

Veja mais detalhes

Fotos: http://aposento.org/sion/images/revistaeditorialonline/anexo.php?id=28329

A policia investiga a causa da morte de Lindemberg mas a
princípio trabalham com a hipótese de suicídio.

Revista Editorial Online.

5.0_BETA dmesg

2008-12-13T10:56:39Z

Just FYI,

---
Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
2006, 2007, 2008
The NetBSD Foundation, Inc. All rights reserved.
Copyright (c) 1982, 1986, 1989, 1991, 1993
The Regents of the University of California. All rights reserved.

NetBSD 5.0_BETA (GENERIC) #0: Sun Dec 14 02:05:49 JST 2008
tsutsui@mirage:/r/work/src/sys/arch/arc/compile/GENERIC
NEC Express 5800/230 R4400 PCI
total memory = 256 MB
avail memory = 243 MB
timecounter: Timecounters tick every 10.000 msec
mainbus0 (root)
cpu0 at mainbus0: MIPS R4400 CPU (0x460) Rev. 6.0 with MIPS R4010 FPC Rev. 0.0
cpu0: 16KB/32B direct-mapped L1 Instruction cache, 48 TLB entries
cpu0: 16KB/32B direct-mapped write-back L1 Data cache
cpu0: 1024KB/64B direct-mapped write-back L2 Unified cache
jazzio0 at mainbus0
timer0 at jazzio0 addr 0xe00001a8
mcclock0 at jazzio0 addr 0xe0004000: mc146818 compatible time-of-day clock
lpt0 at jazzio0 addr 0xe0008000 intr 0
fdc0 at jazzio0 addr 0xe000c000 intr 1
fd0 at fdc0 drive 0: 1.44MB, 80 cyl, 2 head, 18 sec
AD1848 at jazzio0 addr 0xe0010000 intr 2 not configured
sn0 at jazzio0 addr 0xe0001000 intr 3: SONIC Ethernet
sn0: Ethernet address 00:00:4c:a1:30:48
osiop0 at jazzio0 addr 0xe0003000 intr 5: NCR53C710 rev 2, 50MHz, SCSI ID 7
scsibus0 at osiop0: 8 targets, 8 luns per target
osiop1 at jazzio0 addr 0xe0002000 intr 4: NCR53C710 rev 2, 50MHz, SCSI ID 7
scsibus1 at osiop1: 8 targets, 8 luns per target
pckbc0 at jazzio0 addr 0xe0005000 intr 6
pckbd0 at pckbc0 (kbd slot)
wskbd0 at pckbd0 (mux ignored): console keyboard
pms at jazzio0 addr 0xe0005000 intr 7 not configured
com0 at jazzio0 addr 0xe0006000 intr 8: ns16550a, working fifo
com0: txfifo disabled
com1 at jazzio0 addr 0xe0007000 intr 9: ns16550a, working fifo
com1: txfifo disabled
necpb0 at mainbus0
pci0 at necpb0 bus 0
pci0: i/o space, memory space enabled
NEC product 0x0005 (miscellaneous bridge, revision 0x02) at pci0 dev 1 function 0 not configured
Intel 82375EB/SB PCI-EISA Bridge (miscellaneous prehistoric, revision 0x04) at pci0 dev 2 function 0 not configured
tga0 at pci0 dev 3 function 0: DC21030 step C, board type T8-02
tga0: 1024 x 768, 8bpp, Bt485 RAMDAC
tga0: interrupting at int D
wsdisplay0 at tga0 (kbdmux ignored): console (std, vt100 emulation), using wskbd0
timecounter: Timecounter "clockinterrupt" frequency 100 Hz quality 0
timecounter: Timecounter "mips3_cp0_counter" frequency 100000000 Hz quality 100
scsibus0: waiting 2 seconds for devices to settle...
scsibus1: waiting 2 seconds for devices to settle...
sd0 at scsibus0 target 0 lun 0: <IBM, DCAS-34330, S61A> disk fixed
sd0: 4134 MB, 8205 cyl, 6 head, 171 sec, 512 bytes/sect x 8467200 sectors
sd0: sync (100.00ns offset 8), 8-bit (10.000MB/s) transfers
cd0 at scsibus0 target 4 lun 0: <TOSHIBA, XM5701TASUN12XCD, 2395> cdrom removable
cd0: sync (100.00ns offset 8), 8-bit (10.000MB/s) transfers
Kernelized RAIDframe activated
boot device: sd0
root on sd0a dumps on sd0b
root file system type: ffs

---

Note NetBSD/arc 5.0 will have (finally) sysinst(8).

---
Izumi Tsutsui

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2008-06-11T21:13:13Z

,

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pessoas. Que tal iniciar a sua campanha esta semana?

Cordialmente,
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2008-05-21T14:40:16Z

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2007-01-20T06:19:52Z

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Re: clocks on mips

2006-09-08T13:01:37Z

Izumi Tsutsui wrote:

> garrett_damore@... wrote:
>
>
>> How about the following rewrite? I've not tested it yet, but I'm a
>> little concerned about the potential implications of calling hardclock
>> repeatedly to "catch up" lost interrupts. Especially as it effects ntp
>> and timecounters. I'd like to hear opinions on the matter.
>>
>
> I have no idea. I'd like to hear opinions of timecounter guys :-)
>

I talked with Frank about this at some length. It shouldn't matter one
way or the other.

>
>> I also added an evcnt for missed clock interrupts.
>>
>> struct evcnt mips_int5_missed_evcnt =
>> EVCNT_INITIALIZER(EVCNT_TYPE_INTR, NULL, "mips", "missed int 5");
>>
>
> Yeah, I wonder how many interrupts are actually lost.
>

Actually, as I think about this, the only reason we should miss
interrupts is someone is doing splhigh()/splclock() for longer than a
clock tick. That shouldn't happen, outside of someone doing stuff in ddb.

So I'm actually thinking that using the stat counter so we find out if
this is the case or not is the right thing to do -- don't bother with
any of the rest of the handling other than what we already have.

>
>> if (__predict_false(lost > 0)) {
>> next_cp0_clk_intr = new_cnt + curcpu()->ci_cycles_per_hz;
>>
>
> This should be "new_cnt + delta" to keep intervals precisely?
>

I don't think so. I think it is best to get back to a regular interrupt
period. Basically, this ensures that the next interrupt is schedule
for tick cycles ahead. The delta would make the period longer, which
result in an extended time to the next interrupt. (I.e. the next clock
could be several ticks long.)

In any case, I don't think missed interrupts (at least on INT5) happen
in practice outside of ddb, so I don't think we should be worrying about it.

This conclusion is based on the assumption that no port is doing
anything stupid like sharing INT5 with some other device.... and that
driver and kernel code is well behaved and doesn't do
splclock()/splhigh() for long periods of time.

>
>> mips3_cp0_compare_write(next_cp0_clk_intr);
>> for (; lost > 0; lost--) {
>> hardclock(cfp);
>> mips_int5_evcnt.ev_count++;
>>
>
> hardclock(&cp) and mips_int5_missed_evcnt.ev_count?
>

Yes. Doh. Nice catch.

>
>> }
>> }
>>
>
> It's probably better to control hardclock(9) except last call
> not to call spllowersoftclock(9) by tweaking clockframe:
> ---
> if (__predict_false(lost > 0)) {
> int sr;
> next_cp0_clk_intr = new_cnt + delta;
> mips3_cp0_compare_write(next_cp0_clk_intr);
> sr = cf.sr;
> cf.sr &= ~MIPS_SR_INT_IE;
> for (; lost > 0; lost--) {
> hardclock(&cf);
> mips_int5_missed_evcnt.ev_count++;
> }
> cf.sr = sr;
> }
> ---
> But I'd appreciate any comments from interrupt gurus.
>

Actually, the complexity here more than helps convince me that we
shouldn't be doing any of this. It probably never occurs, and we're
more likely to screw it up by trying to handle it.

Many ports have not worried about this before, and seen no ill effects, btw.

-- Garrett
> ---
> Izumi Tsutsui
>

--
Garrett D'Amore, Principal Software Engineer
Tadpole Computer / Computing Technologies Division,
General Dynamics C4 Systems
http://www.tadpolecomputer.com/
Phone: 951 325-2134 Fax: 951 325-2191

Re: clocks on mips

2006-09-08T11:54:48Z

garrett_damore@... wrote:

> How about the following rewrite? I've not tested it yet, but I'm a
> little concerned about the potential implications of calling hardclock
> repeatedly to "catch up" lost interrupts. Especially as it effects ntp
> and timecounters. I'd like to hear opinions on the matter.

I have no idea. I'd like to hear opinions of timecounter guys :-)

> I also added an evcnt for missed clock interrupts.
>
> struct evcnt mips_int5_missed_evcnt =
> EVCNT_INITIALIZER(EVCNT_TYPE_INTR, NULL, "mips", "missed int 5");

Yeah, I wonder how many interrupts are actually lost.

> if (__predict_false(lost > 0)) {
> next_cp0_clk_intr = new_cnt + curcpu()->ci_cycles_per_hz;

This should be "new_cnt + delta" to keep intervals precisely?

> mips3_cp0_compare_write(next_cp0_clk_intr);
> for (; lost > 0; lost--) {
> hardclock(cfp);
> mips_int5_evcnt.ev_count++;

hardclock(&cp) and mips_int5_missed_evcnt.ev_count?

> }
> }

It's probably better to control hardclock(9) except last call
not to call spllowersoftclock(9) by tweaking clockframe:
---
if (__predict_false(lost > 0)) {
int sr;
next_cp0_clk_intr = new_cnt + delta;
mips3_cp0_compare_write(next_cp0_clk_intr);
sr = cf.sr;
cf.sr &= ~MIPS_SR_INT_IE;
for (; lost > 0; lost--) {
hardclock(&cf);
mips_int5_missed_evcnt.ev_count++;
}
cf.sr = sr;
}
---
But I'd appreciate any comments from interrupt gurus.

---
Izumi Tsutsui

Re: clocks on mips

2006-09-08T11:26:34Z

Izumi Tsutsui wrote:
>
>
> BTW, current mips3_clock.c:mips3_clockintr() doesn't handle
> lost clock interrupts properly. (just adjusting the next compare)
> I wonder if it's worth to count how many interrupts were lost
> and call hardclock(9) more than once, like current
> arc/timer.c:statclockintr() and macppc/clock.c:decr_intr() do.
>
How about the following rewrite? I've not tested it yet, but I'm a
little concerned about the potential implications of calling hardclock
repeatedly to "catch up" lost interrupts. Especially as it effects ntp
and timecounters. I'd like to hear opinions on the matter.

I also added an evcnt for missed clock interrupts.

struct evcnt mips_int5_missed_evcnt =
EVCNT_INITIALIZER(EVCNT_TYPE_INTR, NULL, "mips", "missed int 5");

/*
* Handling to be done upon receipt of a MIPS 3 clock interrupt. This
* routine is to be called from the master interrupt routine
* (e.g. cpu_intr), if MIPS INT5 is pending. The caller is
* responsible for blocking and renabling the interrupt in the
* cpu_intr() routine.
*/
void
mips3_clockintr(uint32_t status, uint32_t pc)
{
uint32_t new_cnt, delta, lost = 0;
struct clockframe cf;

cf.pc = pc;
cf.sr = status;

next_cp0_clk_intr += curcpu()->ci_cycles_per_hz;
mips3_cp0_compare_write(next_cp0_clk_intr);

/* Check for lost clock interrupts */
new_cnt = mips3_cp0_count_read();

delta = next_cp0_clk_intr - new_cnt;
while (__predict_false((int32_t)delta < 0)) {
lost++;
delta += curcpu()->ci_cycles_per_hz;
}

/*
* Missed one or more clock interrupts, so let's start
* counting again from the current value. We also trigger
* hardclocks to get the clock interrupt back up to speed.
*
* XXX: What impact will this have on NTP and timecounters?
*/
if (__predict_false(lost > 0)) {
next_cp0_clk_intr = new_cnt + curcpu()->ci_cycles_per_hz;
mips3_cp0_compare_write(next_cp0_clk_intr);
for (; lost > 0; lost--) {
hardclock(cfp);
mips_int5_evcnt.ev_count++;
}
}

hardclock(&cf);

mips_int5_evcnt.ev_count++;

/* caller should renable clock interrupts */
}

>
>> 3) this probably means cleaning up mips3_clock.c somewhat -- the
>> statclock needs to move out of it, and the delay() needs to rename to
>> mips3_delay.
>>
>> 4) for systems that can just use mips3_delay as is, I would use a weak
>> symbol alias so that at link time delay() is resolved to mips3_delay.
>>
>> 5) I'd like to rename cpu_initclocks() to mips3_initclocks() and weak
>> alias it as well.
>>
>
> Yeah, these are what I asked.
>
>
>> 6) I'd like to move the resulting mips3_initclocks() and
>> mips3_clockintr() into a new file, mips3_hardclock.c or
>> mips3_clockintr.c, so that ports which for some reason can't use these
>> (ews4800mips?) don't have to carry the baggage, but can still use the
>> rest of the code in mips3_clock.c
>>
>
> Or to have some __HAVE_MIPS_NO_INT5_CLOCK or something in types.h?
> (and we should get rid of options MIPS3_ENABLE_CLOCK_INTR)
> ---
> Izumi Tsutsui
>

--
Garrett D'Amore, Principal Software Engineer
Tadpole Computer / Computing Technologies Division,
General Dynamics C4 Systems
http://www.tadpolecomputer.com/
Phone: 951 325-2134 Fax: 951 325-2191

Re: clocks on mips

2006-09-08T10:54:05Z

Izumi Tsutsui wrote:

> garrett_damore@... wrote:
>
>
>> It appears that all arc systems have a MIPS 3 clock and can handle clock
>> interrupts on CP0 counter.
>> I think this is probably also true of
>> hpcmips.
>>
>
> hpcmips also supports TX39xx machines and IIRC they are MIPS1.
>
>
>> 1) convert those models that can do it to common mips3 clock code in
>> mips/mips/mips3_clock.c, modulo the following comments
>>
>
> Maybe arc could switch (I guess soda also had the same idea),
> but one concern is that clock frequencies defined in arc/arc/p_*.c
> files for each platform are not confirmed, because unlike sgimips
> most ARC BIOS onarc machines don't have clock frequency info.
> Actually I notice it was wrong for my Express5800/230 while ago.
> We should some clock measurement function like hp300/clock.c,
> but I don't have good idea for it right now.
>
> Note current interupt code in arc is a bit messed up.
> I and soda always discuss that they should be reorganized, but... ;-p
>

Malta currently does this. A realtime clock (if present) can be used to
set the cpu freq in MD code. If you don't have _any_ real-time
reference, then you're hosed anyway.

>
>> 2) this means in the short term, loss of statclock. i propose that the
>> statclock be handled by the external clocks (whatever are present) when
>> they exist. i.e. I'm suggesting that the statclock timer be the
>> "optional" clock, and that the mips3_cp0_clock always be used.
>> statclock/stathz, etc. should be set up by the MD code.
>>
>
> statclock(9) is recommended to have some "variance" in its interval
> for precise statistics (see hp300/clock.c or the Design and
> implementation of 4.4BSD), so I'm not sure if we can use the existing
> external clocks for it because most of them have only fixed interval.
>
> But I don't mind just removing statclock implementations with CPU INT5
> from arc since I can't see particular performance improvement with it.
>

Agreed. statclock() is optional anyway. The issue is that you want to
avoid aliasing the cpu clock and the statclock. With MIPS3 cp0 counter,
if this is a problem, one can just adjust HZ for the port. (I.e. the
cp0 counter is still used, but we write a different value into cp0_compare.

> BTW, current mips3_clock.c:mips3_clockintr() doesn't handle
> lost clock interrupts properly. (just adjusting the next compare)
> I wonder if it's worth to count how many interrupts were lost
> and call hardclock(9) more than once, like current
> arc/timer.c:statclockintr() and macppc/clock.c:decr_intr() do.
>

I'll take a look at it.

I know. Its time to clean it up now. I'm offering to do so.

>
>> 6) I'd like to move the resulting mips3_initclocks() and
>> mips3_clockintr() into a new file, mips3_hardclock.c or
>> mips3_clockintr.c, so that ports which for some reason can't use these
>> (ews4800mips?) don't have to carry the baggage, but can still use the
>> rest of the code in mips3_clock.c
>>
>
> Or to have some __HAVE_MIPS_NO_INT5_CLOCK or something in types.h?
> (and we should get rid of options MIPS3_ENABLE_CLOCK_INTR)
>

Maybe. I don't know. For now putting it in a separate file seems
cleaner than having more garbage in types.h. But that's just my opinion.

-- Garrett
> ---
> Izumi Tsutsui
>

--
Garrett D'Amore, Principal Software Engineer
Tadpole Computer / Computing Technologies Division,
General Dynamics C4 Systems
http://www.tadpolecomputer.com/
Phone: 951 325-2134 Fax: 951 325-2191

Re: clocks on mips

2006-09-08T10:40:19Z

garrett_damore@... wrote:

> It appears that all arc systems have a MIPS 3 clock and can handle clock
> interrupts on CP0 counter.
> I think this is probably also true of
> hpcmips.

hpcmips also supports TX39xx machines and IIRC they are MIPS1.

> 1) convert those models that can do it to common mips3 clock code in
> mips/mips/mips3_clock.c, modulo the following comments

Maybe arc could switch (I guess soda also had the same idea),
but one concern is that clock frequencies defined in arc/arc/p_*.c
files for each platform are not confirmed, because unlike sgimips
most ARC BIOS onarc machines don't have clock frequency info.
Actually I notice it was wrong for my Express5800/230 while ago.
We should some clock measurement function like hp300/clock.c,
but I don't have good idea for it right now.

Note current interupt code in arc is a bit messed up.
I and soda always discuss that they should be reorganized, but... ;-p

> 2) this means in the short term, loss of statclock. i propose that the
> statclock be handled by the external clocks (whatever are present) when
> they exist. i.e. I'm suggesting that the statclock timer be the
> "optional" clock, and that the mips3_cp0_clock always be used.
> statclock/stathz, etc. should be set up by the MD code.

statclock(9) is recommended to have some "variance" in its interval
for precise statistics (see hp300/clock.c or the Design and
implementation of 4.4BSD), so I'm not sure if we can use the existing
external clocks for it because most of them have only fixed interval.

But I don't mind just removing statclock implementations with CPU INT5
from arc since I can't see particular performance improvement with it.

BTW, current mips3_clock.c:mips3_clockintr() doesn't handle
lost clock interrupts properly. (just adjusting the next compare)
I wonder if it's worth to count how many interrupts were lost
and call hardclock(9) more than once, like current
arc/timer.c:statclockintr() and macppc/clock.c:decr_intr() do.

> 3) this probably means cleaning up mips3_clock.c somewhat -- the
> statclock needs to move out of it, and the delay() needs to rename to
> mips3_delay.
>
> 4) for systems that can just use mips3_delay as is, I would use a weak
> symbol alias so that at link time delay() is resolved to mips3_delay.
>
> 5) I'd like to rename cpu_initclocks() to mips3_initclocks() and weak
> alias it as well.

Yeah, these are what I asked.

> 6) I'd like to move the resulting mips3_initclocks() and
> mips3_clockintr() into a new file, mips3_hardclock.c or
> mips3_clockintr.c, so that ports which for some reason can't use these
> (ews4800mips?) don't have to carry the baggage, but can still use the
> rest of the code in mips3_clock.c

Or to have some __HAVE_MIPS_NO_INT5_CLOCK or something in types.h?
(and we should get rid of options MIPS3_ENABLE_CLOCK_INTR)
---
Izumi Tsutsui

clocks on mips

2006-09-08T10:02:13Z

I've been looking at arc.

It appears that all arc systems have a MIPS 3 clock and can handle clock
interrupts on CP0 counter. I think this is probably also true of
hpcmips. For pmax and company, it is probably true for _some_ models.

I'd like to recommend the following:

1) convert those models that can do it to common mips3 clock code in
mips/mips/mips3_clock.c, modulo the following comments

2) this means in the short term, loss of statclock. i propose that the
statclock be handled by the external clocks (whatever are present) when
they exist. i.e. I'm suggesting that the statclock timer be the
"optional" clock, and that the mips3_cp0_clock always be used.
statclock/stathz, etc. should be set up by the MD code.

3) this probably means cleaning up mips3_clock.c somewhat -- the
statclock needs to move out of it, and the delay() needs to rename to
mips3_delay.

4) for systems that can just use mips3_delay as is, I would use a weak
symbol alias so that at link time delay() is resolved to mips3_delay.

5) I'd like to rename cpu_initclocks() to mips3_initclocks() and weak
alias it as well.

6) I'd like to move the resulting mips3_initclocks() and
mips3_clockintr() into a new file, mips3_hardclock.c or
mips3_clockintr.c, so that ports which for some reason can't use these
(ews4800mips?) don't have to carry the baggage, but can still use the
rest of the code in mips3_clock.c

Thoughts?

--
Garrett D'Amore, Principal Software Engineer
Tadpole Computer / Computing Technologies Division,
General Dynamics C4 Systems
http://www.tadpolecomputer.com/
Phone: 951 325-2134 Fax: 951 325-2191

Re: ISA bus-master DMA on arc

2006-07-18T01:37:48Z

[[ sorry for the long lag in my reply ]]

In message: <060624222144.M0101313@...>
Izumi Tsutsui <tsutsui@...> writes:
: imp@... wrote:
:
: > I've had a buslogic ISA controller work in my Deskstation ARCstation
: > (aka rPC44) under OpenBSD/arc. It was a special hacked up driver that
: > pefo wrote to make it work...
:
: Hmm, thanks for your info. It looks rPC44 uses physical address
: for DMA address of ISA bus-master devices.
: (i.e. lower 24bit of KSEG1 address)

This makes a certain amount of sense, because the ISA bus can only
reference 16MB (lower 24bit) via busmaster/dma.

The rPC44 is as close as you can get to a 486 machine with a MIPS
R4400PC bolted in place of the 486. The cache memory is slow (which
is horrible for MIPS performance), and it has nearly all of the warts
of the x86 of the era, plus a few more of its own.

: On the other hand, NEC PCI based machines (my NEC-JC94 etc.)
: use JAZZ DMA TLB for DMA address of PCI bus-master devices.
: I wonder what DMA address should be used for EISA based
: NEC or PICA machines (which have JAZZ-ISA bridge)...

I believe that PICA machines have a different set of constraints on
DMA addresses than the rPC44 does. But I may be getting the PICA
based machines confused with the Deskstation Tyne machines which I
know had a special fast SRAM for DMA.

Warner

Re: ISA bus-master DMA on arc

2006-06-24T07:21:44Z

imp@... wrote:

> I've had a buslogic ISA controller work in my Deskstation ARCstation
> (aka rPC44) under OpenBSD/arc. It was a special hacked up driver that
> pefo wrote to make it work...

Hmm, thanks for your info. It looks rPC44 uses physical address
for DMA address of ISA bus-master devices.
(i.e. lower 24bit of KSEG1 address)

On the other hand, NEC PCI based machines (my NEC-JC94 etc.)
use JAZZ DMA TLB for DMA address of PCI bus-master devices.
I wonder what DMA address should be used for EISA based
NEC or PICA machines (which have JAZZ-ISA bridge)...

Umm, should I implement PCI-EISA bridge part for JC94 first?
---
Izumi Tsutsui

Re: ISA bus-master DMA on arc

2006-06-18T12:35:12Z

In message: <060613212703.M0112582@...>
Izumi Tsutsui <tsutsui@...> writes:
: Has anyone tried any ISA bus-master DMA devices on arc machines?
:
: AHA-1542 on my Express5800/240 EISA (NEC-J96A) hangs during
: probing attached drives, so I wonder if I have to fix ISA DMA stuff
: before I work on EISA stuff to support mlx(4) on EISA on my J96A.
: (Note PIO devices like ep(4) works fine on it)

I've had a buslogic ISA controller work in my Deskstation ARCstation
(aka rPC44) under OpenBSD/arc. It was a special hacked up driver that
pefo wrote to make it work...

Warner

ISA bus-master DMA on arc

2006-06-13T06:27:03Z

Has anyone tried any ISA bus-master DMA devices on arc machines?

AHA-1542 on my Express5800/240 EISA (NEC-J96A) hangs during
probing attached drives, so I wonder if I have to fix ISA DMA stuff
before I work on EISA stuff to support mlx(4) on EISA on my J96A.
(Note PIO devices like ep(4) works fine on it)
---
Izumi Tsutsui

re: 64-bit paddr_t and mmap()?

2006-03-29T23:28:41Z

FWIW, we use 64 bit paddr_t on sparc64, regardless of word size.
(this might be true on sparc, too..?)

Re: 64-bit paddr_t and mmap()?

2006-03-29T13:33:44Z

Matt Thomas wrote:

> Garrett D'Amore wrote:
>> I'm trying to mmap a framebuffer device under evbmips, using a 64-bit
>> paddr_t. (Alchemy PCI space is located in the upper portion of the
>> 36-bit MIPS physical address space.)
>>
>> Anyway, the mmap works fine. I'm able to draw a picture on screen.
>>
>> But when the application exits (and hence does an implicit munmap()), I
>> get a panic in pmap_remove_pv, called from pmap_remove, where it looks
>> like a NULL "pg" pointer is being passed.
>
> That sounds like a bug in the pmap. Not all mapped pages will have a
> corresponding uvm_page (because of being able to map pages outside of
> uvm managed memory). In that case, you just reap the PV entry.
>
> See line 1749 in powerpc/oea/pmap.c for instance.

Yep. I've posted a diff that I think fixes it and send-pr'd it. Still
waiting for the bug number to come back to me. :-)

--
Garrett D'Amore, Principal Software Engineer
Tadpole Computer / Computing Technologies Division,
General Dynamics C4 Systems
http://www.tadpolecomputer.com/
Phone: 951 325-2134 Fax: 951 325-2191

Re: 64-bit paddr_t and mmap()?

2006-03-29T13:28:49Z

Garrett D'Amore wrote:
> I'm trying to mmap a framebuffer device under evbmips, using a 64-bit
> paddr_t. (Alchemy PCI space is located in the upper portion of the
> 36-bit MIPS physical address space.)
>
> Anyway, the mmap works fine. I'm able to draw a picture on screen.
>
> But when the application exits (and hence does an implicit munmap()), I
> get a panic in pmap_remove_pv, called from pmap_remove, where it looks
> like a NULL "pg" pointer is being passed.

That sounds like a bug in the pmap. Not all mapped pages will have a
corresponding uvm_page (because of being able to map pages outside of
uvm managed memory). In that case, you just reap the PV entry.

See line 1749 in powerpc/oea/pmap.c for instance.
--
Matt Thomas email: matt@...
3am Software Foundry www: http://3am-software.com/bio/matt/
Cupertino, CA disclaimer: I avow all knowledge of this message.

64-bit paddr_t and mmap()?

2006-03-29T11:14:15Z

I'm trying to mmap a framebuffer device under evbmips, using a 64-bit
paddr_t. (Alchemy PCI space is located in the upper portion of the
36-bit MIPS physical address space.)

Anyway, the mmap works fine. I'm able to draw a picture on screen.

But when the application exits (and hence does an implicit munmap()), I
get a panic in pmap_remove_pv, called from pmap_remove, where it looks
like a NULL "pg" pointer is being passed.

I'm curious if anyone else has used 64-bit paddr_t's and mmap(), e.g. on
ARC. I'm wondering if maybe I'm trying to do something new, or if there
is some known fault, or if it is known to work on other platforms. Any
info that might help me restrict where I am looking would be useful to
me. :-)

--
Garrett D'Amore, Principal Software Engineer
Tadpole Computer / Computing Technologies Division,
General Dynamics C4 Systems
http://www.tadpolecomputer.com/
Phone: 951 325-2134 Fax: 951 325-2191

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gxemul runs NetBSD/arc (Re: CVS commit: src/sys/arch/arc/jazz)

2005-11-14T05:06:38Z

In article <20051106110917.737FD2DA27@...> on source-changes
I wrote:

> Now gxemul-0.3.6.2 reaches mountroot() sd0 (but can't exec /sbin/init yet).

Umm, it was my fault (wrong /dev files in disk image),
"gxemul -e pica -x netbsd.ramdisk" just works fine.
---
Izumi Tsutsui