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Hello and Season's greetings
I tested it on different versions with cygwin on XP. One of them was
It seems that gnucap doesn't simulate the whole circuit when I connect
two logic gates with
a null voltage source in order to get sel=out1.
It was a big circuit but I took away all the gates that were not
relevant to show what seems a
bug. So I have just now out2 = AND(sel, NOT(sel)) with sel = out1, out1
= AND(in,in) and in = 0
out2 is not as expected : AND(sel=0, notsel=5) = 5 !
Here the Gnucap file
GnuCap File : circuit description
Vttl TTL 0 5
Vin in 0 0
UAND1 out1 0 TTL TTL in in cmos and
Vshunt sel out1 0
UINV notsel 0 TTL TTL sel cmos inv
UAND2 out2 0 TTL TTL notsel sel cmos and
.model cmos LOGIC (vmax=5)
.print tran + V(in)
.print tran + V(out1)
.print tran + V(sel)
.print tran + V(notsel)
.print tran + V(out2)
And the result for tran analysis:
#Time V(in) V(out1) V(sel) V(notsel) V(out2)
0. 0. 0. 0. 5. 5.
100.E-6 0. 0. 0. 5. 5.
If I don't use Vshunt it works but what's the matter ?
And Al, thanks for all the job you have done.
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Re: shunt trouble
On Thursday 30 December 2010, Jacques.Le-Coupanec@...
> I tested it on different versions with cygwin on XP. One of
> them was gnucap-2009-11-10.
> It seems that gnucap doesn't simulate the whole circuit when
> I connect two logic gates with
> If I don't use Vshunt it works but what's the matter ?
Sorry about the delay .. dealing with a crisis totally unrelated
to gnucap ..
There is a bug, ... This circuit works in logic mode, and
apparently there is a bug in the "connectmodule" code, which is
planned for an upgrade anyway to use plugins.
The U devices are logic devices, operating in logic mode, as
logic simulators work. Voltages are created on printout. If
you probe "logic" at the nodes, you will see a code that really
indicates what is happening. The bug is that it didn't properly
initialize and got stuck in a "falling" state, which was never
propagated, after transitioning from the "unknown" state.
Since the floating device is an analog device, that implies
automatic insertion of connectmodules at both ends. The bug is
in one of those.
That is as far as I got.
It hasn't been tested adequately, because I haven't looked at it
years, and have been planning to convert it to plugins, which
requires somewhat of a rewrite anyway.
I don't have a timetable for fixing it.
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